High speed packet-switching networks, such as Asynchronous Transfer Mode (ATM), Internet Protocol (IP), and Gigabit Ethernet, support a multitude of connections to different sessions. Ideally, packet scheduling transfers packets from the different connections with minimal delay while maximizing the use of available bandwidth. Most communication systems have a very limited amount of storage space on the processing integrated circuit (sometimes called a chip) for processing packets and use additional integrated circuits (i.e., external memory chips) to provide larger amounts of external memory for packet storage.
In ATM networks, where packets (usually called cells) are all of a fixed length, the available bandwidth between the processing chip and external memory chip can be used efficiently by using a memory partition size equal to the size of the cells. In variable-length packet-switching networks, however, memory bandwidth may be wasted whenever a packet length is not an integer multiple of the memory partition size.
Like reference symbols in the various drawings indicate like elements.